PLLS=0, LOLIE0=0, CME0=0
MCG Control 6 Register
| VDIV0 | VCO0 Divider |
| CME0 | Clock Monitor Enable 0 (0): External clock monitor is disabled for OSC0. 1 (1): External clock monitor is enabled for OSC0. |
| PLLS | PLL Select 0 (0): FLL is selected. 1 (1): PLLCS output clock is selected (PRDIV0 bits of PLL in control need to be programmed to the correct divider to generate a PLL reference clock in the range of 1 - 32 MHz prior to setting the PLLS bit). |
| LOLIE0 | Loss of Lock Interrrupt Enable 0 (0): No interrupt request is generated on loss of lock. 1 (1): Generate an interrupt request on loss of lock. |